1. Field of the Invention
The present invention relates to methods and apparatus for accurate alignment clock signals, particularly of clock signals in a mixed-signal integrated circuit tester.
2. The Prior Art
Digital integrated circuit (IC) devices are typically tested by applying to pins of the device a pattern of binary stimulus signals in pre-determined patterns and timing relationships. The digital test system looks at the resulting digital output signals of the device and compares them to a pre-defined truth table. A pass or fail decision results, depending on whether the bits (1's and 0's) at the device's output pins match the bits of the truth table during each time interval. Test systems for such devices are flexible and programmable to suit the requirements of the type of device to be tested. An example of a high-speed, programmable digital test system is the ITS 9000FX system commercially available from Schlumberger Technologies, San Jose, Calif.
Other devices to be tested are not purely digital. These devices, known as "mixed-signal" devices, can have both digital and analog signal characteristics. Mixed signal devices often are mostly digital, but cannot be tested as purely digital devices are tested. Mixed signal devices can have pins which require one or more analog signal inputs (e.g., analog-to-digital converters (ADC's)) or one or more analog signal outputs (e.g., digital-to-analog converters (DAC's)) in addition to digital-signal inputs or outputs. Mixed signal devices can have pins which receive or supply digital representations of analog signals (e.g., coder-decoder devices (codecs)).
In a system for testing of purely digital devices, a single master clock is used to synchronize all activities of the tester, such as controlling the event logic which is used to drive pins of a device under test (DUT) and to measure response on pins of the DUT. The ITS 9000FX test system, for example, has a system master clock at a fixed frequency of 312.5 MHz. All activities at the test head are time-aligned based on frequency, known-length periods and fixed-delay lines. Because all is synchronized to a single master clock, the results are repeatable within the accuracy of the system each time a given test is run.
In a mixed-signal test system, each analog channel must have its own clock source which operates asynchronously relative to the system master clock driving the DUT's digital pins. To address mixed-signal testing requirements, fine control over clock frequency is required. The analog-channel clock source must also be deterministic, i.e., the same test results must be obtained each time a given test program is run on the DUT. This means that the phase between an analog-channel clock and the system master clock must be the same each time the test program is run, even though these clocks are operating asynchronously to one another.
FIG. 1 illustrates the need for two "master" clocks in mixed-signal testing. A master clock 100 supplies a clock signal to a frequency divider 105 which in turn supplies a reduced-frequency signal to a sequencer 110. Sequencer 110 supplies a clock signal to the clock input 115 and data bits to a data input 120 of a DUT 125. In the example, DUT 125 is a digital-to-analog converter (DAC) which supplies at an output 130 line an analog signal 135. The test system passes the analog signal through a buffer 140 to a digital-to-analog converter (ADC) 145. To sample the analog signal, ADC 145 needs a clock signal at its clock input 150. A problem arises in that, if the DAC data rate is 100 MHz, traditional sampling would require an unrealistically-high, 200 MHz sampling rate (Nyquist).
One solution is to employ the well-known technique of undersampling, in which the signal is sampled at a lower rate and re-sampled at varying phase relationships to the test pattern as the test pattern is repeatedly applied to the DUT. If undersampling were used in this example to measure 4096 points in 10 nanoseconds (ns), the required clock to the sampler would have a period of 10.00244141 ns, or a frequency of 99,975,591.1 Hz. To derive the 100 M/-Hz clock signal for the DUT and a 99,975,591.1 MHz sampling-clock signal from a single master clock would require a master clock at an impractically-high frequency of 409.5 GHz.
Using two master clocks raises other problems. If two separate clocks are used, they must each have a high resolution (e.g., 0.1 Hz) to achieve a high effective sampling rate (e.g., 1 GHz). The clocks must be phase-locked to one another and, to assure repeatable and deterministic sampling, the phase relationship between the two clocks must not vary from test to test.
In one traditional approach to mixed-signal testing, a first clock supplies a clock-signal used to generate digital events and a second clock supplies a clock-signal for the analog instrument. The analog instrument is thus operating asynchronously to the digital events. Various techniques have been proposed for realigning the asynchronous clock signals, but there is always a remanent error of at least one clock cycle. Testing is therefore not repeatable and deterministic.
Improved methods and apparatus are desired for generating clock signals used in mixed-signal testing.